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description large numbers of relay-based applications require the use of a microprocessor which implements complex system control. in these systems, there is the need for microprocessor logic supply voltage, power-on reset circuitry, and watchdog capabilities. the allegro ? A2550 combines the functions of voltage regulator, watchdog, and reset, as well as three low-side dmos relay driver outputs. primarily targeted at automotive applications, this ic is designed to provide robust performance over extended voltage and temperature ranges. three low-side dmos drivers can drive inductive loads, such as relay coils. each driver integrates rugged voltage clamps which survive automotive load dump pulses up to 48 v. the 40 v rating on vbb also ensures adequate survival in harsh automotive environments. a 5 v linear regulator provides 40 ma of output current, with a tolerance of 2% over the operating temperature range. to enhance the usefulness of the ic in automotive applications, the 5 v regulator output, as well as the three low-side driver outputs are protected against overcurrent conditions. 2550-ds features and benefits ? three independent low-side dmos output drivers ? short-circuit protection of drivers ? eliminates need for flyback diodes on relays ? thermal shutdown ? separate precision 5 v regulator (2%) ? current clamp on 5 v regulator ? 16-pin tssop package with exposed thermal pad ? programmable reset (npor) delay time ? programmable watchdog ? automotive voltage and temperature ranges ? active clamps for automotive load dump specifications ? lead (pb) free relay driver with 5 v regulator for automotive applications continued on the next page? package: 16 pin tssop (suffix lp) with exposed pad typical application approximate scale A2550 out1 out2 out3 pgnd cwd cpor enbat vbb 1 2 3 4 5 6 7 8 in1 in2 in3 lgnd npor wdi en vreg5 16 15 14 13 12 11 10 9 A2550 system logic relays or other inductive loads 0.47 f x7r
relay driver with 5 v regulator for automotive applications A2550 2 allegro microsystems, inc. 115 northeast cutoff, box 15036 worcester, massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com the A2550 also includes power-on reset circuitry (npor) as well as an integrated watchdog circuit. combined, they service the monitoring and reset requirements of a system microprocessor. the A2550 is supplied in a 16-pin tssop package with exposed thermal pad (package lp).the package is lead (pb) free, with 100% matte tin leadframe plating. description (continued) selection guide part number packing A2550klp-t 96 pieces / tube A2550klptr-t 13-in. reel, 4000 pieces / reel absolute maximum ratings characteristic symbol notes rating units supply voltage v bb ?0.3 to 60 v high voltage enable v enbat ?0.3 to 60 v output driver v out continuous rating; outputs off ?1.4 to 48 v output load clamp v out(cl) transient rating 60 v maximum energy at outputs e out single pulse, t j (initial) = 125c 100 mj peak power dissipation at outputs p pk single pulse, t j (initial) = 125c, ? t = 1 ms; see figure 2 for different durations and t j (initial) 1.7 w all other pins ?0.3 to 7 v esd rating ? human body model aec-q100-002; all pins 2.5 kv esd rating ? charged device model aec-q100-011; all pins 1050 v operating ambient temperature t a range k ?40 to 125 oc maximum junction temperature t j (max) 150 oc storage temperature t stg ?55 to 150 oc
relay driver with 5 v regulator for automotive applications A2550 3 allegro microsystems, inc. 115 northeast cutoff, box 15036 worcester, massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com functional block diagram component selection table name suitable characteristics representative device cbb 33 f, 63 v electrolytic united chemi-con egha630e?560mjc5s creg5 0.47 f, 25 v, x7r ceramic cwd, cpor 0.22 f, 16 v, x7r ceramic npor adjustable delay 5v linear regulator vreg5 internal reference v ref vreg5 uvlo enable out1 vbb micro controller hi-v enable vbat vdc coil 1 lgnd wdi enbat en in2 in1 200 k 7 cbb tsd cpor watchdog tsd cwd creg5 0 . 47 f x7r A2550 coil 2 coil 3 relays or other inductive loads hi-v protection pgnd in3 200 k 7 200 k 7 overcurrent protection overcurrent protection overcurrent protection out3 out2 fault logic lgnd and pgnd must be connected externally. a a
relay driver with 5 v regulator for automotive applications A2550 4 allegro microsystems, inc. 115 northeast cutoff, box 15036 worcester, massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com electrical characteristics, ?40c t j 150c, v bb within operating limits, unless otherwise noted characteristics symbol test conditions min. typ. max. units supply vbb operating voltage 1 v bb 7 ? 40 v vbb supply current i bbq all outx off; en = 5 v, v bb = enbat = 14 v ? ? 4 ma i bb all outx on; en = 5 v, v bb = enbat= 14 v ? ? 5 ma i bbs sleep mode, en = enbat = 0 ? ? 10 a logic inputs enbat input voltage 2 v enbat high input level 3.5 ? v bb v low input level 0 ? 1.5 v en, wdi, and inx input voltage v ih high input level 3.5 ? 5.5 v v il low input level 0 ? 1.5 v enbat, en, wdi, inx input voltage hysteresis v ihys 200 ? ? mv enbat input current 2,3 i enbat high input level, v bb = v bb(max) ? ? 400 a high input level, v bb = 14 v ? ? 70 a low input level ?50 ? 10 a en input current 2 i en high input level ? ? 50 a low input level ?50 ? 10 a wdi input current 2 i wdi high input level ? ? 50 a low input level ?10 ? 10 a inx input current 2 i inx high input level ? ? 50 a low input level ?10 ? 10 a drivers propagation delays t p(on) inx change to unloaded output change ? 1 2 s t p(off) inx change to unloaded output change ? 0.5 1 s driver on-resistance r ds(on) i outx = 250 ma, v bb = 14 v ? ? 5 i outx = 250 ma, v bb = 9 v ? ? 5.5 i outx = 250 ma, v bb = 7 v ? ? 6 driver leakage current i dss v outx = 40 v ? ? 10 a diode forward voltage v f i outx = ?250 ma ? ?1.3 ?1.4 v output clamp voltage v cl i outx = 100 a 50 ? 60 v low-side driver overcurrent (o.c.) threshold i out(oc) 275 ? 500 ma blanking time before overcurrent detect t blank i out = 500 ma 2 ? 20 s regulator voltage regulator output voltage v reg5 c reg5 0.47 f (x7r ceramic, esr 0. 5 ), 1 ma i reg5 40 ma 4.9 5.0 5.1 v pass transistor on-resistance 1 r reg5 i reg5 = 40 ma ? ? 55 line regulation voltage v lnr i reg5 = 1 ma ? ? 20 mv load regulation voltage v ldr 1 ma i reg5 40 ma, v bb = 7 v ? ? 100 mv 1 ma i reg5 40 ma, v bb 9 v ? ? 40 mv current limit level 4 i reg5lim v reg5 = 4.63 v, v bb = 7 v 40 ? 150 ma v reg5 = 4.63 v, v bb 9 v 65 ? 200 ma v reg5 = 0 v 65 ? 200 ma under voltage lockout threshold v uvreg5 v reg5 falling 4.25 4.38 4.63 v v reg5 rising 4.36 4.50 4.75 v under voltage lockout hysteresis v uvreg5hys ? 0.12 ? v continued on the next page...
relay driver with 5 v regulator for automotive applications A2550 5 allegro microsystems, inc. 115 northeast cutoff, box 15036 worcester, massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com electrical characteristics, continued ?40c t j 150c, v bb within operating limits, unless otherwise noted characteristics symbol test conditions min. typ. max. units watchdog and power-on reset npor active voltage v npor i npor = 1 ma; v reg5 = 1.5 v; 1.5 v v bb 40 v ? ? 400 mv npor inactive leakage current i npor(off) v npor = 5 v ? ? 10 a cwd and cpor trip voltage v trip(h) v trip(h) = v ref ? 1.2 ? v v trip(l) ? 0.2 ? v cpor charge current i por 2.5 5 7.5 a power-on reset cycle time 5 t por c por = 0.22 f ? 44 ? ms cwd charge current i cwd charging 2.5 5 7.5 a discharging ? 70 ? a thermal protection thermal shut down threshold t tsd ? 175 ? c thermal shut down hysteresis t tsdhys ?15?c 1 see applications information section for operation with v bb < 7 v. for v bb > 24 v, thermal constraints limit regulator current. 2 for input and output current specifications, negative current is defined as coming out of (sourcing) the specified device pin. 3 when v enbat exceeds v bb it is clamped with a diode. (v enbat ? v bb ) 1.2 v at 40 ma. 4 defined as the maximum current level allowed during excessive load condition. 5 see applications information section for calculations. values guaranteed by design, and depend on capacitor tolerances. thermal characteristics may require derating at maximum conditions, see application information characteristic symbol test conditions* value units thermal resistance, junction to pad r jp 2 oc/w thermal resistance, junction to ambient r ja 4-layer pcb based on jedec standard 34 oc/w 2-layer pcb with 2 in. 2 copper both sides, connected by thermal vias 44 oc/w maximum allowable power dissipation p d r ja = 44 oc/w (estimated), 2-layer pcb with 2.0 in. 2 of 2 oz. copper, t a = 125c 0.57 w r ja = 44 oc/w (estimated), 2-layer pcb with 2.0 in. 2 of 2 oz. copper, t a = 85c 1.48 w *additional thermal data available on the allegro web site.
relay driver with 5 v regulator for automotive applications A2550 6 allegro microsystems, inc. 115 northeast cutoff, box 15036 worcester, massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com nonrepetitive output active clamp power dissipation 1 10 100 0.01 0.1 1 10 100 p out (w) t j = 25c t j = 125c dynamic thermal impedance square wave power pulse in a single output stage 0 2 4 6 8 10 12 14 16 18 20 0.01 0.1 1 10 100 time (ms) time (ms) impeda nce (c/w) figure 1. dynamic thermal impedance of an individual output stage during active clamp of an inductive load figure 2. peak power dissipation curves for nonrepetitive clamped outputs. output voltage is clamped during turn-off of inductive loads while current decays.
relay driver with 5 v regulator for automotive applications A2550 7 allegro microsystems, inc. 115 northeast cutoff, box 15036 worcester, massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com thermal resistance (r ja ) vs. copper area on pwb 20 40 60 80 100 120 140 01234 area of copper per zone per layer (in. 2 ) thermal resistance ( c/w ) one layer of copper two layers of copper thermal resistance with 2 oz. copper (additional thermal information is available on the allegro web site) the exposed copper area must be soldered to the exposed thermal pad of the device. for the board with two layers of copper, the copper areas on both sides of the substrate are identical. the two layers are thermally con- nected by vias placed on each ground lead. see jedec standard jesd 51-5 for recommended via geometry.
relay driver with 5 v regulator for automotive applications A2550 8 allegro microsystems, inc. 115 northeast cutoff, box 15036 worcester, massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com pin descriptions en enable pin; logical or with enbat. this logic-level input enables the A2550. if there are no faults, the regulator is live and outputs can be switched. when both the en and enbat pins are held low, the A2550 enters sleep mode. enbat enable pin; logical or with en. same as en, except that this pin is high-voltage protected, and specified up to v bb so it can be tied to the battery or power source. not to exceed v bb because the esd structure places a diode between the enbat and vbb pins. wdi watchdog input. monitors the microcontroller to detect when it stops functioning. this pin is connected to an edge trigger. to avoid a fault, the latter must be triggered before cwd times-out. when not used, wdi is defeated by tying it to npor and shorting cwd. cwd watchdog timer capacitor terminal. used with wdi. a current source charges the external capacitor tied to this pin. a reverse current source discharges the capacitor when either wdi transitions or the high trip voltage, v trip(h) , is reached (see specification table for values). the charge-up time defines the maximum period allowed wdi to toggle before a fault is issued; the charge-down time defines the width of npor pulses issued to wake-up the microcon- troller. npor not power on reset. this active-low pin indicates a fault. except for watchdog faults, npor is held low during the fault state. refer to the fault logic table to determine which faults are latched. watchdog faults generate a train of pulses to ?wake up? the microcontroller. cpor power-on reset timer capacitor terminal. when- ever vreg5 first charges up (at start-up or when a fault is cleared) a ?fault? condition remains in effect until the onboard current source drives cpor to the high trip volt- age, v trip(h) . this allows external circuits, such as a micro- controller, to be initialized before activating the outputs. cpor is defeated by pulling it high to vreg5 with a 50 k resistor. inx input pin. active-high cmos input. internally tied to 200 k pull-down resistors. outx output pin. open drain dmos. clamps to a voltage greater than v bb when an inductive load is switched off. includes current mirror for overcurrent protection. vbb power pin, or ?battery.? specified for automotive volt- ages. vreg5 5 v regulator output. clamped at the current limit level ( i reg5lim ) for excessive loads. as load resistance decreases, vreg5 is pulled below the uvlo level. in that case, a fault is generated (npor low). lgnd logic ground. the reference pin for the logic circuits. must be connected to pgnd externally. pgnd power ground. the reference pin for the outputs (outx). must be connected to lgnd externally. functional description
relay driver with 5 v regulator for automotive applications A2550 9 allegro microsystems, inc. 115 northeast cutoff, box 15036 worcester, massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com 1. 5 v signal to wake up microcontroller. 2. outx enabled with first watchdog pulse. 3. power ramp-up sequence with watchdog active. 4. npor inactive, but outputs not enabled until watchdog detected. timing diagram: initial start-up and exiting sleep mode ~inx wdi cwd npor en or enbat cpor vreg5 vbb internal v ref outx ~inx t por t por internal v ref 1 2 3 4
relay driver with 5 v regulator for automotive applications A2550 10 allegro microsystems, inc. 115 northeast cutoff, box 15036 worcester, massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com 1. missing watchdog detected (wdi low). 2. npor pulses generated periodically. 3. npor inactive, but outputs not enabled until watchdog detected. 4. missing watchdog detected (wdi low, steps 2 and 3 repeat). wdi cwd npor cpor vreg5 internal v ref ~inx outputs enabled t wdr t wd outx 1 2 3 4 timing diagram: watchdog monitoring
relay driver with 5 v regulator for automotive applications A2550 11 allegro microsystems, inc. 115 northeast cutoff, box 15036 worcester, massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com 1. vreg5 undervoltage detected. 2. vreg5 recovers, and after it rises above v uvreg5 + v uvreg5(hys) , uvlo flag is deactivated and cpor recharges. 3. npor inactive, but outputs not enabled until watchdog detected. 4. tsd event detected and npor is activated. when v reg5 v uvreg5 , vreg5 shuts down. 5. tsd flag deactivated (vreg5 allowed to rise; steps 2 and 3 repeat) wdi cwd npor internal vreg5 uvlo cpor vreg5 vbb internal v ref internal v ref outputs enabled ~ inx internal tsd ~inx outx v uvreg5 1 2 3 4 5 timing diagram: vreg5 uvlo and tsd monitoring
relay driver with 5 v regulator for automotive applications A2550 12 allegro microsystems, inc. 115 northeast cutoff, box 15036 worcester, massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com dropout voltage for operation with v bb below the specified range of operat- ing voltages, use the pass transistor on-resistance r reg5 to determine the maximum allowed regulator current, i reg5(max) . this current is limited by the difference between v bb and v reg5 , according to the following equation: reg5 reg5 bb reg5 r v v i ? < (1) figure 3 shows the results of this condition combined with the rated regulator current, in normal operation. note that, although the regulator is specified for normal operation with v bb well above normal automotive voltages, in general thermal constraints will limit maximum opera- tional v bb . fault logic the A2550 offers several protection and fault detection features. the operation of thermal shutdown, watchdog monitoring of the microcontroller, and regulated voltage undervoltage lockout are described in the timing diagrams section. the fault logic is described in table 1. npor the following faults generate a reset state: ? watchdog alarm ? vreg5 falls below the uvlo level in addition, the following conditions cause a low npor signal if the npor pin is pulled up by vreg5 (because these conditions disable vreg5): ? overtemperature (thermal shut down) ? no enable signal (en = enbat = 0) applications information 0 10 20 30 40 50 60 70 0 5 10 15 20 v bb (v) i reg5(max) (ma) table 1. fault logic a inputs outputs mode of operation en or enbat b tsd uvlo watchdog alarm ocx internal 5v vreg5 npor outx 1 0 0 0 0 1 1 1 inx normal operation: outx active for inx active. 10001111z ocx disables outx only. outx latched off until inx removed and reapplied. 1 0 0 1 x 1 1 pulse z npor periodically pulses to attempt reset of microcontroller. 101xx110z npor remains active after uvlo recovers until por delay expires. 1 1xxx1 0 0z 0xxxx0 0offz sleep mode. npor = 0 when pulled up by vreg5 because vreg5 = 0. a x indicates ?don?t care,? z indicates high impedence. b this entry is a logical or of the en and enbat pins. figure 3. current capability of the 5 v regulator (vreg5)
relay driver with 5 v regulator for automotive applications A2550 13 allegro microsystems, inc. 115 northeast cutoff, box 15036 worcester, massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com npor is pulsed for a watchdog fault. for the remaining faults, npor is held low for the duration of the fault. after the fault condition is removed, npor remains low during the t por period. the latter is set by the value of the external capacitor fed by a current source at the cpor pin, according to the following formula: c po r f ms t por ? ? ? ? = 200 (2) the scaling factor is simply derived from the specifications using the typical value of i por : por ref i v v c por por t trip(l) ? = (3) watchdog the watchdog monitors the microcontroller to detect if it locks up. to do so, the watchdog checks for pulses on the watchdog input pin (wdi), and if they are absent for longer than the timeout period, t wd , the watchdog activates npor, which pulses periodically. t wd is proportional to the external capacitor fed by a current source at the cwd pin. the voltage change is 1 v, so using the typical value of i cwd (charging) we have: c wd f ms t wd ? ? ? ? = 200 (4) the pulse width for npor active, t wdr , also scales propor- tionally to the value of the external capacitor at the cwd pin. using the typical value of i cwd (discharging) we have: c wd f ms t wdr ? ? ? ? = 14 (5) see the specification tables for tolerances. when not used, disable watchdog by tying wdi to npor and tying cwd low. table 2 shows watchdog timing for the nominal capacitances listed. output overcurrent when the oc (overcurrent) protection is triggered in a driver, that driver is disabled for self-protection. no other functions are affected; npor and vreg5 operate nor- mally. a disabled output driver remains shut down until the respective inx is brought low, then high again; at which time outx turns on. outx will switch on again the next time inx is applied. if a short-to-battery still exists, the overcur- rent will trip each time inx is reapplied. sleep the A2550 is put to sleep by holding both en and enbat low. in sleep mode all functions are shut down, including vreg5. if the vreg5 regulator is required at all times, dis- able sleep mode by tying enbat to vbb. power limits power dissipation, p d , is limited by thermal constraints. the maximum allowed power dissipation, p d(max) , is found from the formula: ja j(max) t j t = a t r d(max) ( p ) + (6) the maximum junction temperature, t j(max) , and the thermal resistance, r ja , are given in the specification tables. the three main contributors to power dissipation are: ? p bias from the supply bias current ? p reg from the linear regulator voltage drop ? p ls from low-side driver conduction for example, to determine if t j is in an acceptable range, given: r ja = 55c/w , and t a = 125c ; and p bias = v bb i bbq (7) = 14 v 3 ma = 42 mw , and p reg = ( v bb ? v reg5(min) ) i reg5 (8) = (14 v ? 4.9 v) 20 ma= 182 mw , and applications information table 2. timing set by capacitors c ( f) t por (ms) t wd (ms) t wdr (ms) 0.1 20 20 1 0.22 44 44 3 0.47 94 94 7 1 200 200 14
relay driver with 5 v regulator for automotive applications A2550 14 allegro microsystems, inc. 115 northeast cutoff, box 15036 worcester, massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com p ls = ( r ds(on) i 2 ls1 ) + ( r ds(on) i 2 ls2 ) (9) + ( r ds(on) i 2 ls3 ) . because i ls1 = i ls2 = i ls3 = 110 ma , and given that r ds(on) = 5 , then p ls = 3 (5 ) * (110 ma) 2 = 182 mw . given also: p d = p bias + p reg + p ls (10) = 42 mw+ 182 mw+ 182 mw = 406 mw . t j can be calculated by substitution into equation 6: t j = 0.406 w 55c/w +125c = 147c . reverse battery the low-side driver outputs can withstand reverse battery when the load (r loadx ) is connected to limit current. power dissipation (p d = p ls(rvrs) ) is limited by thermal constraints, according to the following formula: f1 i f1 v ls(rvrs) p+ f2 i f2 v + f3 i f3 v = , (11) where: f x i v bb(rvrs) r load x v f x ? = . (12) active clamp on outputs the driver section includes an active clamp that prevents an overvoltage when an inductive load is switched off. zener diodes are connected at the output pins. this removes the need for external freewheeling diodes across inductive loads. the coil current, i coil , is quenched by allowing the output pin voltage, v out x , to exceed the battery voltage at the load, v dc . this applies a negative voltage drop across the load. therefore the current gradient is driven negative, as shown in the following formula: 0 < ? ? = out dc coil l coil r v v di coil dt i coil . (13) the output voltage is clamped to protect the driver. the active clamp works as follows. the voltage at the driver out- put is pushed high by the inductive current. once the clamp voltage, v cl , is reached, a zener diode conducts current to the internal fet gate driver block. therefore, the fet turns partially on, in order to limit any further increase in voltage at the output pin. the output is then held at this clamp volt- age until the current decays to zero, as shown in figure 4. energy loss in the chip, e, may be calculated as follows. load coil resistance, r coil , is usually a significant value, but a worst case scenario takes r coil = 0 for simplicity. with active clamping at v cl , the output current (with initial value i out0 ) is driven low and the upper limit on energy loss in the driver is calculated as: t v i e cl out0 = 2 1 max . (14) from figure 4: t v cl v dc l coil i out0 = ? , (15) and i e v dc v cl l coil out0 = 2 2 ?1 1 ) (1? max / . (16) i out t = i out0 m = ?( v cl ? v dc ) l coil v dc r coil figure 4. output voltage clamping
relay driver with 5 v regulator for automotive applications A2550 15 allegro microsystems, inc. 115 northeast cutoff, box 15036 worcester, massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com a more rigorous derivation, including r coil during the exponential current decay results in: ? ? ? ? ? = coil coil coil cl coil dc l r t r v r v t i exp 1 ) ( ? ? ? ? ? ? ? ? ?? , (17) and coil r () 1 1 ln ? ? cl dc v v t l coil = . (18) energy loss in the driver is: . () () [] cl dc dc cl coil coil dc cl v v v v r l v v e ? ? + = 1 ln 1 1 2 (19) capacitive loads when capacitive loads are applied to the outputs, the constraint described below applies. such is the case, for example, when capacitors are attached to the outputs to protect against esd. larger capacitors protect against larger esd voltages. however, the upper limit on capacitance is determined by the blanking time. the latter allows for spuri- ous current spikes and capacitor discharges to be completed before the overcurrent detection circuit senses the output cur- rent (see t blank in the electrical characteristics table). the blanking time allows a 47 nf capacitor with 20% tolerance and nominal 12 v automotive voltages. terminal list table no. name description 1 in1 activate driver 1 2 in2 activate driver 2 3 in3 activate driver 3 4 lgnd logic ground; must be connected to pgnd externally 5 npor not power-on reset 6 wdi watchdog input 7 en enable (low voltage) 8 vreg5 5v regulator 9 vbb supply voltage 10 enbat enable (high voltage) 11 cpor capacitor terminal for power-on reset cycle time 12 cwd capacitor terminal for watchdog timing 13 pgnd power ground; must be connected to lgnd externally 14 out3 low side driver 3 15 out2 low side driver 2 16 out1 low side driver 1 ? pad exposed pad for enhanced thermal performance 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 out1 out2 out3 pgnd cwd cpor enbat vbb in1 in2 in3 lgnd npor wdi en vreg5 pad pin-out diagram
relay driver with 5 v regulator for automotive applications A2550 16 allegro microsystems, inc. 115 northeast cutoff, box 15036 worcester, massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com 16-pin tssop (suffix lp) with exposed pad the products described here are manufactured under one or more u.s. patents or u.s. patents pending. allegro microsystems, inc. reserves the right to make, from time to time, such de par tures from the detail spec i fi ca tions as may be required to permit improvements in the per for mance, reliability, or manufacturability of its products. before placing an ord er, the user is cautioned to verify that the information being relied upon is current. allegro products are not authorized for use as critical components in life-support devices or sys tems without express written approval. the in for ma tion in clud ed herein is believed to be ac cu rate and reliable. how ev er, allegro microsystems, inc. assumes no re spon si bil i ty for its use; nor for any in fringe ment of patents or other rights of third parties which may result from its use. copyright?2006 allegromicrosystems, inc. 1.20 max .047 0.15 0.00 .006 .000 0.30 0.19 .012 .007 4.5 4.3 .177 .169 6.6 6.2 .260 .244 0.20 0.09 .008 .004 8o 0o 0.75 0.45 .030 .018 1 ref .039 5.1 4.9 .201 .193 c seating plane a b 16x 0.10 [.004] m c a b c 0.10 [.004] 16x 0.65 .026 0.25 .010 2 1 16 gauge plane seating plane b all dimensions reference only, not for tooling use dimensions in millimeters u.s. customary dimensions (in.) in brackets, for reference only (reference jedec mo-153 abt) dimensions exclusive of mold flash, gate burrs, and dambar protrusions exact case and lead configuration at supplier discretion within limits shown a b terminal #1 mark area a exposed thermal pad (bottom surface); dimensions may vary with device c c reference land pattern layout (reference ipc7351 tsop65p640x120-17m); adjust as necessary to meet application process requirements and pcb layout tolerances; when mounting on a multilayer pcb, thermal vias at the exposed thermal pad land can improve thermal dissipation (reference eia/jedec standard jesd51-5) 0.45 nom .018 5.9 nom .232 1.85 nom .073 0.65 nom .026 3 nom .118 3 nom .118 3 nom .118 3 nom .118 2x 0.20 min .008 14x 0.20 min .008

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